This patent had ► Log In grant time compared to others in this category.
Patent grant time can be influenced by many factors. Activities within the USPTO that are beyond the control of patent attornies can influence grant time, but short grant times can also indicate well-written patents and dedicated efforts to respond rapidly to USPTO office actions with strong arguments. Shorter grant times are preferable, and the scores for this section are inverse measures — higher scores are better.
This patent has ► Log In claims compared to others in this category.
The number of claims in a patent is correlated with its strength. Because greater claim counts increase the cost of a patent, more claims can indicate the importance an applicant assigns to a patent. Importantly, some may elect to file claims across multiple patents. A higher score in this metric indicates more claims, relative to others in this category.
This patent has received ► Log In citations from other patents, than others in this category.
Citations from other patents are an important measure of the significance of a patent. More citations indicate that other technologies build on a patent. Higher scores in this metric are better, and indicate more citations from other patents.
This patent referenced ► Log In citations to other patents, than others in this category.
A lower number of citations to other patents can be a sign of diminished patent strength. More citations indicate dependence on more other technologies. Higher scores in this category are better, and indicate fewer citations to other patents.
This patent has ► Log In proximity to basic research compared to others in this category.
Proximity to basic research is measured by comparing the number of citations to non-patent literature among a cohort of patents. Because most non-patent citations are primary research papers, a higher count indicates greater proximity to basic research.
|6,219,908||Method and apparatus for manufacturing known good semiconductor die|
|5,796,264||Apparatus for manufacturing known good semiconductor dice|
|9,324,614||Through via nub reveal method and structure|
|9,196,597||Semiconductor package with single sided substrate design and manufacturing methods thereof|
|9,159,672||Through via connected backside embedded circuit features structure and method|
|9,129,943||Embedded component package and fabrication method|
|9,082,833||Through via recessed reveal structure and method|
|9,059,058||Image sensor device with IR filter and related methods|
|9,054,117||Wafer level package and fabrication method|
|9,048,298||Backside warpage control structure and fabrication method|
|9,013,017||Method for making image sensors using wafer-level processing and associated devices|
|8,981,572||Conductive pad on protruding through electrode semiconductor device|
|8,952,522||Wafer level package and fabrication method|
|8,946,883||Wafer level fan-out package with a fiducial die|
|8,941,222||Wafer level semiconductor package and manufacturing methods thereof|
|8,937,381||Thin stackable package and method|
|8,900,995||Semiconductor device and manufacturing method thereof|
|8,884,424||Semiconductor package with single sided substrate design and manufacturing methods thereof|
|8,796,561||Fan out build up substrate stackable package and method|
|8,791,501||Integrated passive device structure and method|
|8,710,649||Wafer level package and fabrication method|
|8,691,632||Wafer level package and fabrication method|
|8,624,374||Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof|
|8,569,894||Semiconductor package with single sided substrate design and manufacturing methods thereof|
|8,552,548||Conductive pad on protruding through electrode semiconductor device|
|8,501,543||Direct-write wafer level chip scale package|
|8,487,445||Semiconductor device having through electrodes protruding from dielectric layer|
|8,486,764||Wafer level package and fabrication method|
|8,440,554||Through via connected backside embedded circuit features structure and method|
|8,421,226||Device including an encapsulated semiconductor chip and manufacturing method thereof|
|8,405,213||Semiconductor package including a stacking element|
|8,390,130||Through via recessed reveal structure and method|
|8,378,466||Wafer-level semiconductor device packages with electromagnetic interference shielding|
|8,372,689||Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof|
|8,358,001||Semiconductor device packages, redistribution structures, and manufacturing methods thereof|
|8,324,511||Through via nub reveal method and structure|
|8,320,134||Embedded component substrate and manufacturing methods thereof|
|8,298,866||Wafer level package and fabrication method|
|8,294,276||Semiconductor device and fabricating method thereof|
|8,278,746||Semiconductor device packages including connecting elements|
|8,258,633||Semiconductor package and multichip arrangement having a polymer layer and an encapsulant|
|8,193,647||Semiconductor device package with an alignment mark|
|8,188,584||Direct-write wafer level chip scale package|
|8,119,455||Wafer level package fabrication method|
|8,110,916||Chip package structure and manufacturing methods thereof|
|8,035,213||Chip package structure and method of manufacturing the same|
|7,977,163||Embedded electronic component package fabrication method|
|7,932,595||Electronic component package comprising fan-out traces|
|7,902,660||Substrate for semiconductor device and manufacturing method thereof|
|7,723,210||Direct-write wafer level chip scale package|
|7,714,431||Electronic component package comprising fan-out and fan-in traces|
|7,692,286||Two-sided fan-out wafer escape package|
|7,576,436||Structure of wafer level package with area bump|
|7,572,681||Embedded electronic component package|
|7,420,272||Two-sided wafer escape package|
|7,361,533||Stacked embedded leadframe|
|7,247,523||Two-sided wafer escape package|