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Generated January 22, 2018

Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch

Patent Number: 6,845,501

Patent Information

Abstract
A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.
Patent Number: 6,845,501
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,732,235 Cache memory system and method for a digital signal processor
6,651,245 System and method for insertion of prefetch instructions by a compiler
6,578,131 Scaleable hash table for shared-memory multiprocessor system
6,549,995 Compressor system memory organization and method for low latency access to uncompressed memory regions
6,282,706 Cache optimization for programming loops
6,240,488 Prefetching hints
6,237,073 Method for providing virtual memory to physical memory page mapping in a computer operating system that randomly samples state information
6,047,363 Prefetching data using profile of cache misses from earlier code executions
5,742,804 Instruction prefetch mechanism utilizing a branch predict instruction

Patents that cite this patent

Patent Title
9,047,116 Context switch data prefetching in multithreaded computer
9,015,720 Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program
8,996,724 Context switched route look up key engine
8,589,943 Multi-threaded processing with reduced context switching
8,341,352 Checkpointed tag prefetcher
8,141,098 Context switch data prefetching in multithreaded computer
8,099,515 Context switched route look up key engine
8,041,929 Techniques for hardware-assisted multi-threaded processing
8,010,966 Multi-threaded processing using path locks
7,873,816 Pre-loading context states by inactive hardware thread in advance of context switch
7,856,510 Context switched route lookup key engine
7,818,747 Cache-aware scheduling for a chip multithreading processor
7,739,478 Multiple address sequence cache pre-fetching
7,617,499 Context switch instruction prefetching in multithreaded computer
7,606,363 System and method for context switching of a cryptographic engine
7,493,621 Context switch data prefetching in multithreaded computer
7,383,402 Method and system for generating prefetch information for multi-block indirect memory access chains
7,383,401 Method and system for identifying multi-block indirect memory access chains
7,324,106 Translation of register-combiner state into shader microcode
7,103,724 Method and apparatus to generate cache data

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