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Generated January 23, 2018

Method for fabrication of patterns and semiconductor devices

Patent Number: 6,845,497

Patent Information

Patterns for exposure are divided into subdivided regions taking into consideration a scope of an effect of backscattering, the Coulomb effect, and process factors, respectively, on errors in dimensions, and a pattern area occupancy ratio (pattern area density) within the respective subdivided regions is retained, thereby executing exposure with patterns after finding dimensions of pattern modification as the function of the respective pattern area densities. As a result, it becomes possible to fabricate a mask provided with correction for the errors in the dimensions, caused by plural factors such as backscattering, the Coulomb effect, and process factors, and to obtain highly accurate patterns for exposure. Further, use of pattern area density maps enables data processing time necessary for correction to be considerably reduced.
Patent Number: 6,845,497
Issue Date: 2005-01-18

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Patents cited by this patent

Patent Title
6,775,817 Inspection system and semiconductor device manufacturing method
6,721,939 Electron beam shot linearity monitoring
6,657,210 Electron beam exposure method, a method of constructing exposure control data, and a computer-readable medium
6,546,543 Method of displaying, inspecting and modifying pattern for exposure
6,484,300 Systems, methods and computer program products for obtaining an effective pattern density of a layer in an integrated circuit, and for simulating a chemical-mechanical polishing process using the same
6,370,441 Method and apparatus of correcting design-patterned data, method of electron beam and optical exposure, method of fabricating semiconductor and photomask devices
6,243,487 Pattern exposure method using electron beam
5,933,212 Delineating method employing electron ray beam
5,808,310 Electron beam cell projection lithography method for correcting coulomb interaction effects

Patents that cite this patent

Patent Title
9,262,578 Method for integrated circuit manufacturing
8,856,707 Semiconductor device feature density gradient verification
8,232,029 Methods of fabricating a photomask and use thereof
8,105,737 Method of correcting patterns for semiconductor device
8,014,584 Pattern dimension measuring apparatus and pattern area measuring method
7,901,998 Packaging substrate having pattern-matched metal layers
7,861,210 Exposure data generator and method thereof
7,810,066 Irradiation pattern data generation method, mask fabrication method, and plotting system
7,774,736 Method and apparatus for providing optical proximity features to a reticle pattern for deep sub-wavelength optical lithography
7,669,174 Pattern generation method and charged particle beam writing apparatus
7,564,049 Pattern drawing system, electrically charged beam drawing method, photomask manufacturing method, and semiconductor device manufacturing method
7,500,219 Exposure data generator and method thereof
7,313,769 Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
7,240,313 Method for analyzing material density variations on a multi-layer printed circuit board
7,205,078 Method for generating backscattering intensity on the basis of lower layer structure in charged particle beam exposure, and method for fabricating semiconductor device utilizing this method
7,174,526 Accurate density calculation with density views in layout databases
7,045,801 Charged beam exposure apparatus having blanking aperture and basic figure aperture

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