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Generated January 22, 2018

Method for generating design constraints for modules in a hierarchical integrated circuit design system

Patent Number: 6,845,494

Patent Information

Abstract
What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.
Patent Number: 6,845,494
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,453,446 Timing closure methodology
6,415,426 Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design
6,367,060 Method and apparatus for clock tree solution synthesis based on design constraints
6,167,557 Method and apparatus for logic synthesis employing size independent timing optimization
6,145,117 Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
6,086,621 Logic synthesis constraints allocation automating the concurrent engineering flows
5,903,471 Method for optimizing element sizes in a semiconductor device

Patents that cite this patent

Patent Title
9,275,186 Optimization for circuit migration
9,165,098 Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs
9,152,742 Multi-phase models for timing closure of integrated circuit designs
9,122,826 Method and apparatus for performing compilation using multiple design flows
8,990,758 Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
8,977,995 Timing budgeting of nested partitions for hierarchical integrated circuit designs
8,977,994 Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints
8,972,920 Re-budgeting connections of a circuit design
8,966,422 Median line based critical timing path optimization
8,935,642 Methods for single pass parallel hierarchical timing closure of integrated circuit designs
8,832,633 Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
8,806,408 Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby
8,762,909 System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)
8,683,407 Hierarchical design flow generator
8,640,066 Multi-phase models for timing closure of integrated circuit designs
8,589,838 M/A for performing incremental compilation using top-down and bottom-up design approaches
8,539,423 Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
8,539,419 Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
8,539,402 Systems for single pass parallel hierarchical timing closure of integrated circuit designs
8,539,401 Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
8,522,179 System and method for managing timing margin in a hierarchical integrated circuit design process
8,365,113 Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
8,302,042 Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
8,296,690 Method and arrangement providing for implementation granularity using implementation sets
8,281,269 Method of semiconductor integrated circuit device and program
8,261,220 Path preserving design partitioning with redundancy
8,239,805 Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
8,141,010 Method and arrangement providing for implementation granularity using implementation sets
7,992,122 Method of placing and routing for power optimization and timing closure
7,873,927 Partitioning a large design across multiple devices
7,823,112 Method, software and system for ensuring timing between clocked components in a circuit
7,730,437 Method of full semiconductor chip timing closure
7,644,383 Method and system for correcting signal integrity crosstalk violations
7,627,836 OPC trimming for performance
7,512,918 Multimode delay analysis for simplifying integrated circuit design timing models
7,437,695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices
7,370,302 Partitioning a large design across multiple devices
7,322,019 Electronic circuit designing method and apparatus, and storage medium
7,318,211 Method for physical placement of an integrated circuit based on timing constraints
7,120,892 Process for adjusting data structures of a floorplan upon changes occurring
7,117,466 System and method for correlated process pessimism removal for static timing analysis

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