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Generated January 22, 2018

Memory sub-system error cleansing

Patent Number: 6,845,472

Patent Information

Abstract
A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or cleansing operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the cleansing logic initiates a cleansing routine in response to an event such as an operator instruction or a periodic schedule. By implementing the cleansing operation, the system does not rely on external READ commands to verify data integrity. Further, a monitoring device is coupled between the cleansing logic and a memory scheduler. The monitoring device provides a feed back mechanism from which to vary the frequency of certain memory requests such as the cleansing and scrubbing operations. The cleansing routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the cleansing routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.
Patent Number: 6,845,472
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,223,301 Fault tolerant memory
6,101,614 Method and apparatus for automatically scrubbing ECC errors in memory via hardware
6,098,132 Installation and removal of components of a computer
6,076,183 Method of memory error correction by scrubbing
5,768,560 Dynamically configurable memory system having a programmable controller including a frequency multiplier to maintain memory timing resolution for different bus speeds

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