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Generated January 23, 2018

Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register

Patent Number: 6,845,460

Patent Information

Abstract
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
Patent Number: 6,845,460
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,748,549 Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
6,691,214 DDR II write data capture calibration
6,622,103 System for calibrating timing of an integrated circuit wafer tester
6,606,041 Predictive timing calibration for memory devices
6,434,081 Calibration technique for memory devices
6,418,537 Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL
6,374,361 Skew-insensitive low voltage differential receiver
6,101,152 Method of operating a synchronous memory device
6,067,592 System having a synchronous memory device
6,038,195 Synchronous memory device having a delay time register and method of operating same
6,035,365 Dual clocked synchronous memory device having a delay time register and method of operating same
6,028,898 Signal regenerator
6,016,282 Clock vernier adjustment
5,953,263 Synchronous memory device having a programmable register and method of controlling same
5,917,760 De-skewing data signals in a memory system
5,841,580 Integrated circuit I/O using a high performance bus interface

Patents that cite this patent

Patent Title
9,159,382 Method and apparatus for timing adjustment
9,111,645 Request-command encoding for reduced-data-rate testing
7,542,322 Buffered continuous multi-drop clock ring
7,509,515 Method and system for communicated client phase information during an idle period of a data bus
7,310,400 Data recovery device and method
7,127,003 Method and apparatus for communicating information using different signaling types
7,095,661 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
7,043,652 Calibration method and memory system

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