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Generated January 23, 2018

System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines

Patent Number: 6,845,459

Patent Information

An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
Patent Number: 6,845,459
Issue Date: 2005-01-18

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Patents cited by this patent

Patent Title
6,531,974 Controlling time delay
6,518,812 Discrete delay line system and method
6,480,047 Reduced jitter phase lock loop using a technique multi-stage digital delay line
6,462,623 Method and apparatus for PLL with improved jitter performance
6,445,231 Digital dual-loop DLL design using coarse and fine loops
6,285,172 Digital phase-locked loop circuit with reduced phase jitter frequency
6,268,753 Delay element that has a variable wide-range delay capability
6,265,916 Clock multiplier circuit capable of generating a high frequency clock signal from a low frequency input clock signal
6,212,126 Semiconductor device including clock generation circuit capable of generating internal clock stably
6,204,732 Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units
6,163,174 Digital buffer circuits
6,131,168 System and method for reducing phase error in clocks produced by a delay locked loop
6,121,808 DLL calibrated phase multiplexer and interpolator
6,101,197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges
6,094,082 DLL calibrated switched current delay interpolator
6,047,346 System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
6,011,732 Synchronous clock generator including a compound delay-locked loop
5,923,715 Digital phase-locked loop circuit
5,870,003 High frequency phase-locked loop circuit having reduced jitter
5,854,797 Tester with fast refire recovery time
5,844,954 Fine resolution digital delay line with coarse and fine adjustment stages
5,808,478 Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading
5,774,403 PVT self aligning internal delay line and method of operation

Patents that cite this patent

Patent Title
9,316,729 Systems and methods for providing trigger timing
8,437,428 Digital frequency locked delay line
8,271,825 Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch
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7,835,205 Delay stage-interweaved analog DLL/PLL
7,702,942 Method for generating adjustable MRAM timing signals
7,692,598 Method and apparatus for transmitting and receiving time-domain radar signals
7,675,454 System, method, and computer program product providing three-dimensional visualization of ground penetrating radar data
7,664,216 Digital frequency locked delay line
7,652,619 Systems and methods using multiple down-conversion ratios in acquisition windows
7,649,492 Systems and methods for providing delayed signals
7,453,301 Method of and circuit for phase shifting a clock signal
7,453,297 Method of and circuit for deskewing clock signals in an integrated circuit
7,449,939 Bias generator with feedback control
7,447,106 Delay stage-interweaved analog DLL/PLL
7,443,761 Loop filtering for fast PLL locking
7,336,084 Delay lock circuit having self-calibrating loop
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7,177,205 Distributed loop components
7,111,185 Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit
7,009,407 Delay lock circuit having self-calibrating loop

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