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Generated January 22, 2018

Low power cache architecture

Patent Number: 6,845,432

Patent Information

Abstract
In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may reduced. The reduction in this size of the memory cluster reduces the power needed for an address decoder to address sets within the bank.
Patent Number: 6,845,432
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,684,298 Dynamic reconfigurable memory hierarchy
6,608,476 Method and apparatus for reducing power consumption
6,528,974 Method and apparatus for reducing power consumption
6,449,694 Low power cache operation through the use of partial tag comparison
6,442,667 Selectively powering X Y organized memory banks
6,427,188 Method and system for early tag accesses for lower-level caches in parallel with first-level cache
6,307,281 System and method for reducing power dissipation in a circuit
6,219,796 Power reduction for processors by software control of functional units
6,115,793 Mapping logical cache indexes to physical cache indexes to reduce thrashing and increase cache size
6,041,401 Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus
5,931,951 Computer system for preventing cache malfunction by invalidating the cache during a period of switching to normal operation mode from power saving mode
5,901,322 Method and apparatus for dynamic control of clocks in a multiple clock processor, particularly for a data cache
5,870,616 System and method for reducing power consumption in an electronic circuit
5,809,532 Data processor with cache and method of operation
5,805,907 System and method for reducing power consumption in an electronic circuit
5,781,783 Method and apparatus for dynamically adjusting the power consumption of a circuit block within an integrated circuit
5,682,515 Low power set associative cache memory with status inhibit of cache data output

Patents that cite this patent

Patent Title
8,762,652 Cache coherency protocol in a data processing system
8,706,974 Snoop request management in a data processing system
8,606,998 System and method for instruction-based cache allocation policies
8,423,721 Cache coherency protocol in a data processing system
8,301,928 Automatic wakeup handling on access in shared memory controller
8,230,176 Reconfigurable cache
7,930,484 System for restricted cache access during data transfers and method thereof
7,805,619 Circuit technique to reduce leakage during reduced power mode
7,483,333 Memory device and method having banks of different sizes
7,418,553 Method and apparatus of controlling electric power for translation lookaside buffer
7,360,023 Method and system for reducing power consumption in a cache memory
7,290,089 Executing cache instructions in an increased latency mode
7,193,927 Memory device and method having banks of different sizes
7,177,223 Memory device and method having banks of different sizes
7,167,989 Processor and methods to reduce power consumption of processor components
7,127,560 Method of dynamically controlling cache size
7,082,075 Memory device and method having banks of different sizes
7,010,656 Method and apparatus for memory management
6,971,034 Power/performance optimized memory controller considering processor power states

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