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Generated January 23, 2018

Flexible interrupt controller that includes an interrupt force register

Patent Number: 6,845,419

Patent Information

Abstract
A flexible interrupt controller (28) that includes an interrupt force register (120) is presented. Hardware interrupts (102) that are presently asserted by their respective hardware sources are stored in an interrupt source register (110) included in the interrupt controller (28). An independent interrupt force register (120) stores currently pending software interrupts (104) which may be asserted through the execution of software routines by the central processing unit (CPU) (12) within the data processing system (10). In one embodiment, each bit location in the interrupt source register (110) has a corresponding bit location in the interrupt force register (120), and each bit in the interrupt force register (120) is logically OR-ed with the corresponding bit in the interrupt source register (110). Results of the logical OR operation are stored in an interrupt pending register (160) and the contents of the interrupt pending register (160) is bit wise OR-ed together in order to generate an interrupt request signal (174) provided to the CPU (12).
Patent Number: 6,845,419
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,625,149 Signaled receiver processing methods and apparatus for improved protocol processing
6,412,081 System and method for providing a trap and patch function to low power, cost conscious, and space constrained applications
5,987,601 Zero overhead computer interrupts with task switching
5,937,199 User programmable interrupt mask with timeout for enhanced resource locking efficiency

Patents that cite this patent

Patent Title
9,189,283 Task launching on hardware resource for client
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8,909,835 Computer system and method of controlling computer system
8,838,852 Programmable interrupt routing system
8,762,615 Dequeue operation using mask vector to manage input/output interruptions
8,738,830 Hardware interrupt processing circuit
8,639,850 Addressing scheme to allow flexible mapping of functions in a programmable logic array
8,397,043 Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product
8,135,894 Methods and systems for reducing interrupt latency by using a dedicated bit
7,913,255 Background thread processing in a multithread digital signal processor
7,882,293 Interrupt masking control
7,793,025 Hardware managed context sensitive interrupt priority level control
7,739,438 Method for priority-encoding interrupts and vectoring to interrupt code
7,584,316 Packet manager interrupt mapper
7,464,210 Data processing system having a data transfer unit for converting an integer into a floating-point number when tranferring data from a peripheral circuit to a memory
7,266,630 CPU contained LSI
7,162,559 System for controlling interrupts between input/output devices and central processing units

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