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Generated January 20, 2018

Method and system for a host processor to broadcast data to instruction or data memories of several processors in a multi-processor integrated circuit

Patent Number: 6,845,412

Patent Information

Abstract
A system and method are presented for an external host processor to distribute data to memory devices associated with multiple digital signal processors (DSPs) within an integrated circuit “system on a chip.” A host processor interface in the multi-processor integrated circuit responds to commands from the host processor and provides access to the memory devices. A control register in the interface is directly accessible by the host processor, and is used to generate various control signals in response to host processor commands. A data control register in the interface has a field of write enable bits that directly control write accessibility of the memory devices—if a designated write-enable bit within the data control register is set, the corresponding memory devices are write enabled. An extended address bit in the control register is used to select either instruction or data memory for write access.
Patent Number: 6,845,412
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,553,525 Method and apparatus for selectively enabling and disabling functions on a per array basis
6,353,874 Method and apparatus for controlling and caching memory read operations in a processing system
6,212,610 Memory protection mechanism for a distributed shared memory multiprocessor with integrated message passing support
6,003,120 Method and apparatus for performing variable length processor write cycles
5,968,114 Memory interface device
5,890,006 Apparatus for extracting instruction specific bytes from an instruction

Patents that cite this patent

Patent Title
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8,327,114 Matrix processor proxy systems and methods
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7,966,481 Computer system and method for executing port communications without interrupting the receiving computer
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7,937,557 System and method for intercommunication between computers in an array
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7,870,365 Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
7,617,383 Circular register arrays of a computer
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7,516,320 Distributed processing architecture with scalable processing layers
7,380,151 Apparatus and method for asynchronously clocking the processing of a wireless communication signal by multiple processors
7,373,121 Apparatus and method for processing a deterministic data flow associated with a wireless communication signal
7,218,730 System and method for analysis and filtering of signals in a telecommunications network

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