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Generated January 20, 2018

Interpage prologue to protect virtual address mappings

Patent Number: 6,845,353

Patent Information

In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
Patent Number: 6,845,353
Issue Date: 2005-01-18

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Biographical Information

Executive Summary


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Patent Grant Time

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Patent Claims

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Patents cited by this patent

Patent Title
6,415,379 Method and apparatus for maintaining context while executing translated instructions
6,363,336 Fine grain translation discrimination
6,163,764 Emulation of an instruction set on an instruction set architecture transition
5,832,205 Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed

Patents that cite this patent

Patent Title
8,464,033 Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream
8,438,548 Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version
8,418,153 Method for integration of interpretation and translation in a microprocessor
8,413,162 Multi-threading based on rollback
8,019,983 Setting a flag bit to defer event handling to a safe point in an instruction stream
7,904,891 Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur
7,840,788 Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register
7,761,857 Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts
7,644,210 Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system
7,404,181 Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold

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