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Generated January 23, 2018

Method and mechanism for improved performance analysis in transaction level models

Patent Number: 6,845,341

Patent Information

Abstract
A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.
Patent Number: 6,845,341
Issue Date: 2005-01-18

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Citations

Patents cited by this patent

Patent Title
6,618,839 Method and system for providing an electronic system design with enhanced debugging capabilities
6,581,191 Hardware debugging in a hardware description language
6,530,054 Method and apparatus for test generation during circuit design
6,470,482 METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION
6,347,388 Method and apparatus for test generation during circuit design
6,182,258 Method and apparatus for test generation during circuit design
6,163,763 Method and apparatus for recording and viewing error data generated from a computer simulation of an integrated circuit
6,075,932 Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
5,953,519 Method and system for generating electronic hardware simulation models

Patents that cite this patent

Patent Title
8,868,397 Transaction co-validation across abstraction layers
8,719,742 Conversion of circuit description to an abstract model of the circuit
8,577,818 Automatic model evolution
8,522,177 Method and apparatus for electronic system function verification at two levels
8,489,525 Automatic model evolution
8,468,475 Conversion of circuit description to an abstract model of the circuit
8,417,504 Conversion of circuit description to a transaction model
8,386,973 Behavioral synthesis apparatus, method, and program having test bench generation function
8,336,009 Method and apparatus for electronic system function verification at two levels
8,122,398 Conversion of circuit description to an abstract model of the circuit
8,091,051 Behavioral synthesis apparatus, method, and program having test bench generation function
8,020,124 Various methods and apparatuses for cycle accurate C-models of components
7,865,345 Simulation apparatus and method
7,440,882 Method and system for analyzing transaction level simulation data of an integrated circuit design

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